A liquid crystal display device is now being widely used as a display device including a display device substrate. The liquid crystal display device is used in various electrical devices because of its characteristics such as a small and slim profile, a low electrical power consumption, and light weight. Particularly, an active matrix liquid crystal display device having switching elements each arranged in a pixel is being widely used in OA apparatuses such as a PC, AV apparatuses such as a TV, mobile apparatuses such as a cellular phone, for example.
FIG. 12 is a schematic view showing a conventional display device substrate used in a liquid crystal display device. FIG. 12(a) is a plan view thereof. FIG. 12(b) is a cross-sectional view of the substrate taken along line X8-Y8 in FIG. 12(a). A conventional display device substrate 11 includes: on a main surface of a substrate 1110, a base layer 1111; pixel switching transistors 1113a and 1113b; gate electrodes 1119a and 1119b; a plurality of gate wirings 1118; a storage capacitor lower electrode 1122; a plurality of storage capacitor wirings (storage capacitor upper electrodes) 1121; a pixel date storage capacitor element 1120; a plurality of data wirings 1115; a first interlayer insulating film 1151 having contact holes 1154a and 1154b; a second interlayer insulating film 1152 having a through-hole 1155; a pixel electrode 1116; and a connection part 1117 for connecting the pixel electrode 1116 to a source-drain region of the transistor 1113b, as shown in FIG. 12.
The display device substrate 11 has, on the main surface of the substrate 1110, a structure where the base layer 1111, the semiconductor layer 1130, the gate insulating film 1112, the first wiring layer 1141, the first interlayer insulating film 1151, the second wiring layer 1142, the second interlayer insulating film 1152, and the pixel electrode 1116 are stacked in this order from the substrate 1110 side.
The pixel date storage capacitor element 1120 is composed of the storage capacitor lower electrode 1122 formed in the semiconductor layer and the storage capacitor wiring 1121 constituted by the first wiring layer 1141. That is, a region facing the storage capacitor lower electrode 1122 of the storage capacitor wiring 1121 functions as a storage capacitor upper electrode. The gate wiring 1118 is formed from a high melting point metal or polysilicon, with a high resistivity. The date wiring 1115 is arranged to cross with (perpendicular to) the gate wiring 1118 and the storage capacitor wiring 1121 and to be insulated with these wirings 1118 and 1121 by the first interlayer insulating film 1151. In addition, the first interlayer insulating film 1151 is formed from an inorganic insulating material including silicon (for example, SiO2, SiN, SiNO) by plasma CVD, sputtering, and the like. The data wiring 1115 and the connection part 1117, which are positioned in the second wiring layer 1142, are formed by patterning a conductive layer formed on the first interlayer insulating film 1151 by photolithography.
For such a liquid crystal display device, improvements in characteristics such as an increase in resolution, improvements in ratio of a pixel effective area (high aperture ratio) and in display qualities, and a reduction in electrical power consumption, are needed.
Under such a circumstance, for example, Patent Document 1 discloses the following liquid crystal panel with build-in driver capable of fitting to fine pixel. The panel includes a matrix array and a driving circuit for driving this matrix array on the same transparent substrate. The matrix array includes a gate wiring that is electrically connected to a gate of a thin film transistor; and a first data wiring that is electrically connected to a source of the transistor through a connection hole of a lower interlayer insulating film; and a second data wiring that is electrically connected to the first data wiring surface and forms a multi-wiring layer structure. The driving circuit includes a three-wiring layer structure where the layers are separated from each other by the lower interlayer insulating film and the upper interlayer insulating film. At least one of the first and second data wirings is formed from the same material as a material for anyone of the wiring layers arranged in the driving circuit (for example, refer to Patent Document 1).
In addition, Patent Document 2 discloses the following driver built-in active matrix display panel which can improve a display grade by adopting a structure meeting functions for pixel regions and a driving circuit. In a pixel region partitioned by a scanning line that is electrically connected to a gate electrode of a thin film transistor and a signal line with a high etching resistance that is electrically connected to a source of the thin film transistor through a first connection hole that is formed on the surface side of a lower interlayer insulating film formed on the upper layer side of the scanning line and that penetrate the lower interlayer insulating film and a gate insulating film of the thin film transistor, the panel includes: an upper interlayer insulating film that is formed on the upper layer side of the signal line; and a pixel electrode being formed on the surface side of this upper interlayer insulating film such that an end of the pixel electrode is close to an upper position of a signal line partitioning the corresponding pixel region, the pixel electrode being electrically connected to a drain of the thin film transistor through a second connection hole that penetrates the upper interlayer insulating film, the lower interlayer insulating film, and the gate insulating film.
Like the display panels disclosed in Patent Documents 1 and 2, a peripheral circuit such as a driver may be integrally formed on a substrate constituting a display device. In addition to high-resolution, improvements in ratio of a pixel effective area (high aperture ratio) and in display qualities and a reduction in electrical power consumption, such a display device needs downsizing of the peripheral circuit. So a technology of forming a multi-layered wiring that is formed in a peripheral circuit is being researched and developed.
With respect to this multi-layered wiring technology, for example, Patent Document 3 discloses the following wiring substrate as a technology of providing a wiring substrate and a semiconductor device, each including a multi-layered wiring that can be formed through a smaller number of steps and having a small circuit with high functions. The wiring substrate includes: a first wiring formed on a substrate with an insulating surface; a first interlayer insulating film formed to cover the first wiring; a second wiring formed on the first interlayer insulating film; a second interlayer insulating film formed to cover the second wiring; a third wiring formed on the second interlayer insulating film; a first contact hole that is formed in the first interlayer insulating film and electrically connects the first wiring to the second wiring; a second contact hole that is formed in the second interlayer insulating film and electrically connects the second wiring to the third wiring, and the third wiring has a width larger than that of the first and second wirings, the second wiring has a width larger than that of the first wiring, and the second contact hole has a diameter or an area larger than that of the first contact hole.
[Patent Document 1]
    Japanese Kokai Publication No. H-05-150264[Patent Document 2]    Japanese Kokai Publication No. H-06-34996[Patent Document 3]    Japanese Kokai Publication No. 2005-72573